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9596c?at42?05/2013 features ? configurations: ? comms mode ? standalone mode ? number of keys: ? comms mode: 1 ? 7 keys (or 1 ? 6 keys plus a guard channel) ? standalone mode: 1 ? 4 keys plus a fixed guard channel on key 0 ? number of i/o lines: ? standalone mode: 5 outputs ? technology: ? patented spread-spectrum charge-transfer ? key outline sizes: ? 6 mm x 6 mm or larger (panel thickness dependent); widely different sizes and shapes possible ? layers required: ? one ? electrode materials: ? etched copper; silver; carbon; indium tin oxide (ito) ? panel materials: ? plastic; glass; composites; painted su rfaces (low particle density metallic paints possible ? panel thickness: ? up to 10 mm glass; up to 5 mm plastic (electrode size dependent) ? key sensitivity: ? comms mode: individually settable via simple commands over i 2 c-compatible interface ? standalone mode: settings are fixed ? interface: ? i 2 c-compatible slave mode (400 khz). discrete detection outputs ? signal processing: ? self-calibration ? auto drift compensation ? noise filtering ? adjacent key suppression ? (aks ? ) ? up to three groups possible ? power: ? 1.8 v ? 5.5 v ? package: ? 14-pin soic rohs compliant ic ? 20-pin vqfn rohs compliant ic atmel at42qt1070 seven-channel qtouch ? touch sensor ic datasheet
2 at42qt1070 [datasheet] 9596c?at42?05/2013 1. pinouts and schematics 1.1 pinout configuration ? comms mode (14-pin soic) 1.2 pinout configurat ion ? standalone m ode (14-pin soic) vdd mode (vss) reset sda change key2 key1 key0 1 2 3 4 5 6 78 9 10 11 12 13 14 qt1070 scl key6 key3 vss key5 key4 vdd mode (vdd) reset out0 out4 key2 key1 key0 1 2 3 4 5 6 78 9 10 11 12 13 14 qt1070 out3 out2 key3 vss out1 key4
3 at42qt1070 [datasheet] 9596c?at42?05/2013 1.3 pinout configuration ? comms mode (20-pin vqfn) 1.4 pinout configurat ion ? standalone m ode (20-pin vqfn) nc nc vss vdd nc key4 key3 key2 key1 key0 mode (vss) sda 1 2 3 4 5 11 12 13 14 15 20 19 18 17 16 6 7 8 10 9 qt1070 reset change scl key6 key5 nc nc nc nc nc vss vdd nc key4 key3 key2 key1 key0 mode (vdd) out0 1 2 3 4 5 11 12 13 14 15 20 19 18 17 16 6 7 8 10 9 qt1070 reset out4 out3 out2 out1 nc nc nc
4 at42qt1070 [datasheet] 9596c?at42?05/2013 1.5 pin descriptions i input only o output only, push-pull od open drain output p ground or power table 1-1. pin listin gs (14-pin soic) pin name (comms mode) name (standalone mode) type description if unused, connect to... 1 vdd vdd p power ? 2 mode mode i mode selection pin comms mode ? connect to vss standalone mode ? connect to vdd ? 3 sda out0 od comms mode ? i 2 c data line standalone mode ? open drain output for guard channel open 4 reset reset i reset ? has internal pull-up 60 k ? resistor open 5 change out4 od change line for controlling the communications flow comms mode ? connect to change line standalone mode ? connect to output open 6 scl out3 od comms mode ? connect to i 2 c clock standalone mode ? connect to output open 7 key6 out2 o/od comms mode ? connect to key 6 standalone mode ? connect to output open 8 key5 out1 o/od comms mode ? connect to key 5 standalone mode ? connect to output open 9 key4 key4 o key 4 open 10 key3 key3 o key 3 open 11 key2 key2 o key 2 open 12 key1 key1 o key 1 open 13 key0 key0 o key 0 open 14 vss vss p ground ?
5 at42qt1070 [datasheet] 9596c?at42?05/2013 i input only o output only, push-pull od open drain output p ground or power table 1-2. pin listin gs (20-pin vqfn) pin name (comms mode) name (standalone mode) type description if unused, connect to... 1 key4 key4 o key 4 open 2 key3 key3 o key 3 open 3 key2 key2 o key 2 open 4 key1 key1 o key 1 open 5 key0 key0 o key 0 open 6 nc nc ? not connected ? 7 nc nc ? not connected ? 8 vss vss p ground ? 9 vdd vdd p power ? 10 nc nc ? not connected ? 11 mode mode i mode selection pin comms mode ? connect to vss standalone mode ? connect to vdd ? 12 sda out0 od comms mode ? i 2 c data line standalone mode ? open drain output for guard channel open 13 reset reset i reset ? has internal pull-up 60 k ? resistor open 14 change out4 od change line for controlling the communications flow comms mode ? connect to change line standalone mode ? connects to output open 15 scl out3 od comms mode ? connect to i 2 c clock standalone mode ? connect to output open 16 key6 out2 o/od comms mode ? connect to key 6 standalone mode ? connect to output open 17 key5 out1 o/od comms mode ? connect to key 5 standalone mode ? connect to output open 18 nc nc ? not connected ? 19 nc nc ? not connected ? 20 nc nc ? not connected ?
6 at42qt1070 [datasheet] 9596c?at42?05/2013 1.6 schematics figure 1-1. typical circuit ? comms (14-pin soic) figure 1-2. typical circuit ? standalone (14-pin soic) rs6 c1 k4 r scl rs5 rs4 rs3 rs2 rs1 k3 k2 k1 1 qt1070 mode (vss) 2 sda 3 reset 4 change 5 scl 6 key6 7 key5 8 key4 9 key3 10 key2 11 key1 12 key0 13 14 vss rs0 k0 vss vdd change sda reset k5 k6 vdd scl vdd vss r sda vdd r chg r rst r out2 c1 k4 r out3 r out1 rs4 rs3 rs2 rs1 k3 k2 k1 1 out0 3 reset 4 out4 5 out3 6 out2 7 out1 8 key4 9 key3 10 key2 11 key1 12 key0 13 vss rs0 k0 vss r out4 vdd reset c out1 c out2 c out3 vss c out4 c out0 14 vss qt1070 vdd vss outputs outputs r out0 mode (vdd) 2 c out1, 2 3 and are optional c out0 4 and are optional r1 vdd
7 at42qt1070 [datasheet] 9596c?at42?05/2013 figure 1-3. typical circui t ? comms (20-pin vqfn) figure 1-4. typical circuit ? standalone (20-pin vqfn) for component values in figure 1-1 , 1-2 , 1-3 , and 1-4 , check the following sections: section 3.1 on page 12 : series resistors (rs0 ? rs6 for comms mode and rs0 ? rs4 for standalone mode) section 3.2 on page 12 : led traces section 3.4 on page 12 : power supply (voltage levels) section 4.4 on page 14 : sda, scl pull-up resistors rs6 c1 k4 rs5 rs4 rs3 rs2 rs1 k3 k2 k1 9 qt1070 scl 15 sda 12 reset 13 change 14 key6 16 key5 17 key4 1 key3 2 key2 3 key1 4 key0 5 8 vss rs0 k0 vss vdd k5 k6 r scl vdd vdd vss 11 mode (vss) n/c n/c 18 n/c 19 n/c 20 n/c 7 n/c 6 10 change sda reset r sda vdd r chg r rst rs out2 k4 rs out3 rl out1 rs4 rs3 rs2 rs1 k3 k2 k1 out0 12 reset 13 out4 14 out3 15 out2 16 out1 17 key4 1 key3 2 key2 3 key1 key0 5 vss rs0 k0 r out4 reset c out1 c out2 c out3 vss c out4 c out0 8 qt1070 vss outputs outputs n/c n/c 18 n/c 19 n/c 20 n/c 7 n/c 6 10 4 r out0 vss c1 9 vss vdd vdd mode (vdd) 11 c out1, 2 3 and are optional c out0 4 and are optional r1 vdd
8 at42qt1070 [datasheet] 9596c?at42?05/2013 2. overview 2.1 introduction the at42qt1070 (qt1070) is a digita l burst mode charge-transfer (qt ? ) capacitive sensor driver. the device can sense from one to seven keys, dependent on mode. the qt1070 includes all signal processing functions necessary to provide stable sensing under a wide variety of changing conditions, and the outputs are fully debounced. only a few external parts are required for operation and no external cs capacitors are required. the qt1070 modulates its bursts in a spread-spectrum fashion in order to heavily suppress the effects of external noise, and to suppress rf emissions. the qt1070 uses a dual-pulse method of acquisition. this provides greater noise immunity and eliminates the need for external sampli ng capacitors, allowing touch sensing using a single pin. 2.2 modes 2.2.1 comms mode the qt1070 can operate in comms mode where a host can communicate with the device via an i 2 c bus. this allows the user to configure settings for th reshold, adjacent key suppression ( aks), detect integrator, low power (lp) mode, guard channel and max time on for keys. 2.2.2 standalone mode the qt1070 can operate in a standalone mode where an i 2 c interface is not required. to enter standalone mode, connect the mode pin to vdd before powering up the qt1070. in standalone mode, the start-up values are hard coded in firmware and cannot be changed. the default start-up values are used. this means that key detection is repo rted via their respective ios. the guard channel feature is automatically implemented on key 0 in standalone mode. this means that this channel gets priority over all other keys going into touch. 2.3 keys dependent on mode, the qt1070 can have a minimum of one key and a maximum of seven keys. these can be constructed in different shapes and sizes. see ?features? on page 1 for the recommended dimensions. ? comms mode ? 1 to 7 keys (or 1 to 6 keys plus guard channel) ? standalone mode ? 1 to 4 keys plus a guard channel unused keys should be disabled by setting the averaging factor to zero (see section 5.9 on page 18 ). the status register can be read to determine the touch status of the corresponding key. it is recommended using the open-drain change line to detect when a change of status has occurred. 2.4 input/output (io) lines there are no io lines in comms mode. in standalone mode pins out0 ? out4 can be used as open drain outputs for driving leds. 2.5 acquisition/low power mode (lp) there are 255 different acquisition times possible. these are controlled via the lp mode byte (see section 5.11 on page 19 ) which can be written to via i 2 c communication. lp mode controls the intervals between acquisition meas urements. longer intervals consume lower power but have an increased response time. during calibration, touch and dur ing the detect integrator (di) period, the lp mode is temporarily set to lp mode 1 for a faster response.
9 at42qt1070 [datasheet] 9596c?at42?05/2013 the qt1070 operation is based on a fixed cycle time of approximately 8 ms. the lp mode setting indicates how many of these periods exist per measurement cycle. for ex ample, if lp mode = 1, there is an acquisition every cycle (8 ms). if lp mode = 3, there is an acquisition every 3 cycles (24 ms). if a high averaging factor (see section 5.9 on page 18 ) setting is selected then the acquisition time may exceed 8 ms. lp settings above mode 32 (256 ms) result in slower thermal drift compensation and should be avoided in applications where fast thermal transients occur. 2.6 adjacent key suppre ssion (aks) technology the device includes the atmel- patented adjacent key supp ression (aks) technology, to allow the use of tightly spaced keys on a keypad with no loss of selectability by the user. there can be up to three aks groups, implemented so that only one key in the group may be reported as being touched at any one ti me. once a key in a particular aks group is in detect no other key in that group can go into detect. only when the key in detect goes out of detection can another key go into detect state. the keys which are members of the aks groups can be set (see section 5.9 on page 18 ). keys outside the group may be in detect simultaneously. 2.7 change line (comms mode only) the change line is active low and signals when there is a change of state in the detection or input key status bytes. it is cleared (allowed to float high) when the host reads the status bytes. if the status bytes change back to their original state before the host has read the status bytes (for example, a touch followed by a release), the change line will be held low. in this case, a read to any memory location will clear the change line. the change line is open-drain and should be connected via a 47 k ? resistor to vdd. it is necessary for minimum power operation as it ensures that the qt1070 can sleep for as long as possible. communications wake up the qt1070 from sleep causing a higher power cons umption if the part is randomly polled. note: the change line is pulled low 100 ms after power-up or reset. 2.8 types of reset 2.8.1 external reset an external reset logic line can be used if desired, fed into the reset pin. however, under most conditions it is acceptable to tie reset to vdd. 2.8.2 soft reset the host can cause a device reset by writing a nonzero value to the reset byte. this soft reset triggers the internal watchdog timer on a 125 ms interval. after 125 ms the device resets and wakes again. the device nacks any attempts to communicate with it during the first 30 ms of its initialization period. 2.9 calibration writing a non-zero value to the calibration byte can force a recalibration at any time. this can be useful to clear out a stuck key condition after a prolonged period of uninterrupted detection. note: a calibrate command clears all key status bits and the overflow bit (until it is checked on the next cycle).
10 at42qt1070 [datasheet] 9596c?at42?05/2013 2.10 guard channel a guard channel to help prevent false detection is available in both modes. this is fixed on key 0 for standalone mode and programmable for comms mode. guard channel keys should be more sensitive than the other keys (physically bigger). because the guard channel key is physically bigger it becomes more susceptible to noise so it has a higher averaging factor (see section 5.9 on page 18 ) and a lower threshold (see section 5.8 on page 18 ) than the other keys. in standalone mode it has an averaging factor of 16 and a threshold of 10 counts. a channel set as the guard channel (there can only be one) is prioritised when the filtering of keys going into detect is taking place. so if a normal key is filtering into touch (touch present but di has not been reached) and the key set as the guard key begins filtering in, then the normal key? s filter is reset and the guard key filters in first. the guard channel is connected to a sensor pad which detects the presence of touch and overrides any output from the other keys. figure 2-1. guard channel example 2.11 signal processing 2.11.1 detect threshold the device detects a touch when the signal has crossed a threshold level and remained there for a specified number of counts (see section 5.10 on page 19 ). this can be altered on a key-by-key basis using the key threshold i 2 c commands. in standalone mode the detect threshold is set to a fixed value of 10 counts of change with respect to the internal reference level for the guard channel and 20 counts for the other four keys. the reference level has the ability to adjust itself slowly in accordance with the drift compensation mechanism. the drift mechanism will drift toward touch at a rate of 160 ms 18 = 2.88 seconds and away from touch at a rate of 160 ms 6 = 0.96 seconds. the 160 ms is based on 20 8 ms cycles. if the cycle time exceeds 8 ms then the overall times will be extended to match. 2.11.2 detect integrator the device features a fast detection integrator counter (di filter), which acts to filter out noise at the small expense of a slower response time. the di filter requires a programmable number of consecutive samples confirmed in detection before the key is declared to be touched. the minimum number for the di filter is 2. settings of 0 and 1 for the di also default to 2. the di is also implemented when a touch is removed. this uses the fast out di option. when bit 5 of address 53 is set the a key filters out with an integrator of 4. g u ard ch anne l
11 at42qt1070 [datasheet] 9596c?at42?05/2013 2.11.3 cx limitations the recommended range for key capacitance cx is 1 pf ? 30 pf. larger values of cx will give reduced sensitivity. 2.11.4 max on duration if an object or material obstructs the sense pad the signal may rise enough to create a detection, preventing further operation. to prevent this, the sensor includes a timer which monitors detections. if a detection exceeds the timer setting the sensor performs a key recalibration. this is known as the max on duration feature and is set to approximately 30 s in standalone mode. in comms mode this feature can be changed by setting a value in the range 1 ? 255 (160 ms ? 40,800 ms) in steps of 160 ms. a setting of 0 disables the max on duration recalibration feature. note: if bit 4 of address 53 is clear then a recalibration of all keys occurs on max on duration, otherwise individual key recalibration occurs. 2.11.5 positive recalibration if a keys signal jumps in the negative direction (with respect to its reference) by more than the positive recalibration setting (4 counts), then a recalibration of that key takes place. 2.11.6 drift hold time drift hold time (dht) is used to restrict drift on all keys while one or more keys are activated. dht restricts the drifting on all keys until approximately four seconds after all touches have been removed. this feature is particularly useful in cases of high-density keypads where touching a key or hovering a finger over the keypad would cause untouched keys to drift, and therefore create a sensitivity shift, and ultimately inhibit touch detection. 2.11.7 hysteresis hysteresis is fixed at 12.5% of the detect threshold. when a key enters a detect state once the di count has been reached, the nthr value is changed by a small amount (12.5% of nthr) in the direction away from touch. this is done to affect hysteresis and so makes it less likely a key will dither in and out of detect. nthr is restored once the key drops out of detect.+
12 at42qt1070 [datasheet] 9596c?at42?05/2013 3. wiring and parts 3.1 rs resistors series resistors rs (rs0 ? rs6 for comms mode and rs0 ? rs4 for standalone mode) are in line with the electrode connections and should be used to limit electrostatic di scharge (esd) currents and to suppress radio frequency interference (rfi). series resistors are recommended fo r noise reduction. they should be approximately 4.7 k ? to 20 k ? each. 3.2 led traces and ot her switching signals digital switching signals near the sense lines induce transi ents into the acquired signals, deteriorating the signal-to- noise (snr) performance of the device. such signals should be routed away from the sensing traces and electrodes, or the design should be such that these lines are not sw itched during the course of signal acquisition (bursts). led terminals which are multiplexed or switched into a floati ng state, and which are within, or physically very near, a key (even if on another nearby pcb) should be bypassed to ei ther vss or vdd with at least a 10 nf capacitor. this is to suppress capacitive coupling effects which can induce false signal shifts. the bypass capacitor does not need to be next to the led, in fact it can be quite distant. the bypass capacitor is noncritical and can be of any type. led terminals which are constantly connected to vss or vdd do not need further bypassing. 3.3 pcb cleanliness modern no-clean flux is generally compatible with capacitive sensing circuits. if a pcb is reworked in any way, clean it thoroughly to remove all traces of the flux residue around the capacitive sensor components. dry it thoroughly before any further testing is conducted. 3.4 power supply see section 6.2 on page 22 for the power supply range. if the power supply fluctuates slowly with temperature, the device tracks and compensates for these changes automatically with only minor changes in sensitivity. if the supply voltage drifts or shifts quickly, the drift compensation mechanism is not able to keep up, causing sensitivity anomalies or false detections. the usual power supply considerations with qt parts apply to the device. the power should be clean and come from a separate regulator if possible. however, this device is designed to minimize the effects of unstable power, and except in extreme conditions should not require a separate low dropout (ldo) regulator. it is assumed that a larger bypass capacitor (such as1 f) is somewhere else in the power circuit; for example, near the regulator. caution: if a pcb is reworked in any way, it is highly likely that the behavior of the no-clean flux will change. this can mean that the flux chang es from an inert material to one that can absorb moisture and dram atically affect capacitive measurements due to additional leakage currents. if so, t he circuit can become erratic and exhibit poor environmental stability. caution: a regulator ic shared with other logic can result in erratic operation and is not advised. a single ceramic 0.1 f bypass capacitor, with short traces, should be placed very close to the power pins of the ic. failure to do so can result in device oscillation, high current consumption and erratic operation.
13 at42qt1070 [datasheet] 9596c?at42?05/2013 4. i 2 c communications (comms mode only) 4.1 i 2 c protocol 4.1.1 protocol the i 2 c protocol is based around access to an address table (see table 5-1 on page 15 ) and supports multibyte reads and writes. the maximum clock rate is 400 khz. see section a. on page 29 for an overview of i 2 c bus operation. 4.1.2 signals the i 2 c interface requires two signals to operate: ? sda - serial data ? scl - serial clock a third line, change , is used to signal when the device has seen a change in the status byte: change : open-drain, active low when any capacitive key has changed state since the last i 2 c read. after reading the two status bytes, this pin floats (high) again if it is pulled up with an external resistor. if the status bytes change back to their original state before the host has read the status bytes (for example, a touch followed by a release), the change line is held low. in this case, a read to any memory location clears the change line. 4.2 i 2 c address there is one preset i 2 c address of 0x1b . this is not changeable. 4.3 data read/write 4.3.1 writing data to the device the sequence of events required to write data to the device is shown next. 1. the host initiates the transfer by sending the start condition 2. the host follows this by sending the slave address of the device together with the write bit. 3. the device sends an ack. table 4-1. description of write data bits key description s start condition sla+w slave address plus write bit a acknowledge bit memaddress target memory address within device data data to be written p stop condition sla +w me m address aa s data a p h ost to de v i c ede v i c e tx to h ost
14 at42qt1070 [datasheet] 9596c?at42?05/2013 4. the host then sends the memory address within the device it wishes to write to. 5. the device sends an ack if the write address is in the range 0x00 ? 0x7f , otherwise it sends a nack. 6. the host transmits one or more data bytes; each is acknowledged by the device (unless trying to write to an invalid address). 7. if the host sends more than one data byte, they are written to consecutive memory addresses. 8. the device automatically increments the target memory address after writing each data byte. 9. after writing the last data byte, the host should send the stop condition. note: the host should not try to write to addresses outside the range 0x20 to 0x39 because this is the limit of the device internal memory address. 4.3.2 reading data from the device the sequence of events required to read data from the device is shown next. 1. the host initiates the transfer by sending the start condition 2. the host follows this by sending the slave address of the device together with the write bit. 3. the device sends an ack. 4. the host then sends the memory address within the device it wishes to read from. 5. the device sends an ack if the address to be read from is less than 0x80 otherwise it sends a nack). 6. the host must then send a stop and a start condition followed by the slave address again but this time accompanied by the read bit. note: alternatively, instead of step 6 a repeated start can be sent so the host does not need to relinquish control of the bus. 7. the device returns an ack, followed by a data byte. 8. the host must return either an ack or nack. 1. if the host returns an ack, the device subsequently transmits the data byte from the next address. each time a data byte is transmitted, the device automat ically increments the internal address. the device continues to return data bytes until the host responds with a nack. 2. if the host returns a nack, it should then terminate the transfer by issuing the stop condition. 9. the device resets the internal address to the location indicated by the memory address sent to it previously. therefore, there is no need to send the memory address again when reading from the same location. note: reading the 16-bit reference and signal values is not an automatic operation; reading the first byte of a 16- bit value does not lock the other byte. as a result glitches in the reported value may be seen as values increase from 255 to 256, or decrease from 256 to 255. 4.4 sda, scl the i 2 c bus transmits data and clock with sda and scl respectively. they are open-drain; that is i 2 c master and slave devices can only drive these lines low or leave them open. the termination resistors pull the line up to vdd if no i 2 c device is pulling it down. the termination resistors commonly range from 1 k ? to 10 k ? and should be chosen so that the rise times on sda and scl meet the i 2 c specifications (1 s maximum). standalone mode: if i 2 c communications are not required, then standalone mode can be enabled by connecting the mode pin to vdd. see section 2.4 on page 8 for more information. sla +w me m address aa s s sla + ra a p h ost to de v i c ede v i c e tx to h ost p a a data 1 data 2 data n
15 at42qt1070 [datasheet] 9596c?at42?05/2013 5. setups 5.1 introduction the device calibrates and processes signals using a number of algorithms specifically designed to provide for high survivability in the face of adverse environmental challenges. user-defined setups are employed to alter these algorithms to suit each application. these setups are loaded into the device over the i 2 c serial interfaces. in standalone mode these settings are fixed to predetermined values. table 5-1. internal register address allocation address use bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w 0 chip id major id (= 2) minor id (= e) r 1 firmware version firmware version number r 2 detection status calibrate overflow ? ? ? ? ? touch r 3 key status reserved key 6 key 5 key 4 key 3 key 2 key 1 key 0 r 4 ? 5 key signal 0 key signal 0 (msbyte) ? key signal 0 (lsbyte) r 6 ? 7 key signal 1 key signal 1 (msbyte) ? key signal 1 (lsbyte) r 8 ? 9 key signal 2 key signal 2 (msbyte) ? key signal 2 (lsbyte) r 10 ? 11 key signal 3 key signal 3 (msbyte) ? key signal 3 (lsbyte) r 12 ? 13 key signal 4 key signal 4 (msbyte) ? key signal 4 (lsbyte) r 14 ? 15 key signal 5 key signal 5 (msbyte) ? key signal 5 (lsbyte) r 16?17 key signal 6 key signal 6 (msbyte) ? key signal 6 (lsbyte) r 18 ? 19 reference data 0 reference data 0 (msbyte) ? reference data 0 (lsbyte) r 20 ? 21 reference data 1 reference data 1 (msbyte) ? reference data 1 (lsbyte) r 22 ? 23 reference data 2 reference data 2 (msbyte) ? reference data 2 (lsbyte) r 24 ? 25 reference data 3 reference data 3 (msbyte) ? reference data 3 (lsbyte) r 26 ? 27 reference data 4 reference data 4 (msbyte) ? reference data 4 (lsbyte) r 28 ? 29 reference data 5 reference data 5 (msbyte) ? reference data 5 (lsbyte) r 30?31 reference data 6 reference data 6 (msbyte) ? reference data 6 (lsbyte) r 32 nthr key 0 negative threshold level for key 0 r/w 33 nthr key 1 negative threshold level for key 1 r/w 34 nthr key 2 negative threshold level for key 2 r/w 35 nthr key 3 negative threshold level for key 3 r/w 36 nthr key 4 negative threshold level for key 4 r/w 37 nthr key 5 negative threshold level for key 5 r/w 38 nthr key 6 negative threshold level for key 6 r/w 39 ave/aks key 0 adjacent key suppression level for key 0 r/w 40 ave/aks key 1 adjacent key suppression level for key 1 r/w
16 at42qt1070 [datasheet] 9596c?at42?05/2013 5.2 address 0: chip id major id: reads back as 2 minor id: reads back as e 5.3 address 1: firmware version firmware version : this shows the 8-bit firmware version 1.5 ( 0x15 ). 41 ave/aks key 2 adjacent key suppression level for key 2 r/w 42 ave/aks key 3 adjacent key suppression level for key 3 r/w 43 ave/aks key 4 adjacent key suppression level for key 4 r/w 44 ave/aks key 5 adjacent key suppression level for key 5 r/w 45 ave/aks key 6 adjacent key suppression level for key 6 r/w 46 di key 0 detection integrator counter for key 0 r/w 47 di key 1 detection integrator counter for key 1 r/w 48 di key 2 detection integrator counter for key 2 r/w 49 di key 3 detection integrator counter for key 3 r/w 50 di key 4 detection integrator counter for key 4 r/w 51 di key 5 detection integrator counter for key 5 r/w 52 di key 6 detection integrator counter for key 6 r/w 53 fo/mo/guard no fastoutdi/ max cal/guard channel r/w 54 lp low power (lp) mode r/w 55 max on duration maximum on duration r/w 56 calibrate calibrate r/w 57 reset reset r/w table 5-1. internal register address allocation (continued) address use bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w table 5-2. chip id address b7 b6 b5 b4 b3 b2 b1 b0 0 major id minor id table 5-3. firmware version address b7 b6 b5 b4 b3 b2 b1 b0 1 firmware version
17 at42qt1070 [datasheet] 9596c?at42?05/2013 5.4 address 2: detection status calibrate: this bit is set during a calibration sequence. overflow: this bit is set if the time to acquire all key signals exceeds 8 ms. touch: this bit is set if any keys are in detect. 5.5 address 3: key status key0 ? 6: bits 0 to 6 indicate which keys are in detection, if any. touched keys report as 1, untouched or disabled keys report as 0. 5.6 address 4 ? 17: key signal key signal: addresses 4 ? 17 allow key signals to be read for each key, starting with key 0. there are two bytes of data for each key. these are the key?s 16-bit key signals which are accessed as two 8-bit bytes, stored msbyte first. these addresses are read-only. table 5-4. detection status address b7 b6 b5 b4 b3 b2 b1 b0 2 calibrate overflo w ? ? ? ? ? touch table 5-5. key status address b7 b6 b5 b4 b3 b2 b1 b0 3 reserved key6 key5 key4 key3 key2 key1 key0 table 5-6. key signal address b7 b6 b5 b4 b3 b2 b1 b0 4 msbyte of key signal for key 0 5 lsbyte of key signal for key 0 6?17 msbyte/lsbyte of key signal for keys 1 ? 6
18 at42qt1070 [datasheet] 9596c?at42?05/2013 5.7 address 18 ? 31: reference data reference data: addresses 18 ? 31 allow reference data to be read for each key, starting with key 0. there are two bytes of data for each key. these are the key?s 16-bit reference data which is accessed as two 8-bit bytes, stored msbyte first. these addresses are read-only. 5.8 address 32 ? 38: ne gative threshold (nthr) nthr keys 0 ? 6: these 8-bit values set the threshold value for each key to register a detection. default: 20 counts note: do not use a setting of 0 as this causes a key to go into detection when its signal is equal to its reference. 5.9 address 39 ? 45: averaging fact or/adjacent key s uppression (ave/aks) ave 0?5: the averaging factor (ave) is the number of pulses which are added together and averaged to get the final signal value for that channel. for example, if ave = 8 then 8 adc samples are taken and added together. the result is divided by the original number of pulses (8). if sixteen pulses are used then the result is divided by sixteen. this provides a better signal-to-noise ratio but requires longer acquire times. values for ave are restricted internally to 1, 2, 4, 8, 16 or 32. default: 8 (in standalone mode key 0 is 16) aks 0 ? 1: these bits control which keys are included in an aks group. there can be up to three groups, each containing any number of keys (up to the maximum allowed for the mode). each key can have a value be tween 0 and 3, which assigns it to an aks group of that number. a key may only go into detect when it has the largest signal change of any key in its group. a value of 0 means the key is not in any aks group. default: 0x01 table 5-7. reference data address b7 b6 b5 b4 b3 b2 b1 b0 18 msbyte of reference data for key 0 19 lsbyte of reference data for key 0 20?31 msbyte/lsbyte of refe rence data for keys 1 ? 6 table 5-8. nthr address b7 b6 b5 b4 b3 b2 b1 b0 32?38 negative threshold for keys 0 ? 6 table 5-9. ave/aks address b7 b6 b5 b4 b3 b2 b1 b0 39?45 ave5 ave4 ave3 ave2 ave1 ave0 aks1 aks0
19 at42qt1070 [datasheet] 9596c?at42?05/2013 5.10 address 46 ? 52: detection integrator (di) detection integrator: addresses 46 ? 52 allow the di level to be set for each key. this 8-bit value controls the number of consecutive measurements that must be confirmed as having passed the key threshold before that key is registered as being in detect. the minimum value for the di filter is 2. settings of 0 and 1 for the di also default to 2 because a minimum of two consecutive measurements must be confirmed. default: 4 5.11 address 53: fastoutd i/max cal/guard channel fo: fast out di ? when bit 5 is set then a key filters out with an integrator of 4. could have a di in of 100 but filter out with di of 4 (global setting for all keys). max cal: if this bit is clear then all keys recalibrate after a max on duration timeout, otherwise only the key with the incorrect timing gets recalibrated. guard channel: bits 0 ? 3 are used to set a key as the guard channel (which gets priority filtering). valid values are 0 ? 6, with any larger value disabling the guard key feature. 5.12 address 54: low power (lp) mode table 5-10. detection integrator address b7 b6 b5 b4 b3 b2 b1 b0 46?52 detection integrator table 5-11. max cal/guard channel address b7 b6 b5 b4 b3 b2 b1 b0 53 ? fo max cal guard channel table 5-12. lp mode address b7 b6 b5 b4 b3 b2 b1 b0 54 low power mode
20 at42qt1070 [datasheet] 9596c?at42?05/2013 lp mode: this 8-bit value determines the number of 8 ms in tervals between key measurements. longer intervals between measurements yield a lower power consumption but at the expense of a slower response to touch. default: 2 (16 ms between key acquisitions) 5.13 address 55: max on duration max on duration: this is a 8-bit value which determines how long any key can be in touch before it recalibrates itself. a value of 0 turns max on duration off. default: 180 (160 ms 180 = 28.8s) setting time 0 8ms 1 8ms 2 16 ms 3 24 ms 4 32 ms ? ? 254 2.032s 255 2.040s table 5-13. max time on address b7 b6 b5 b4 b3 b2 b1 b0 55 max on duration setting time 0 off 1 160 ms 2 320 ms 3 480 ms 4 640 ms 255 40.8s
21 at42qt1070 [datasheet] 9596c?at42?05/2013 5.14 address 56: calibrate writing any nonzero value into this address triggers the device to start a calibration cycle. the calibrate flag in the detection status register is set when the calibra tion begins and clears when the calibration has finished. 5.15 address 57: reset writing any nonzero value to this address triggers the device to reset. table 5-14. calibrate address b7 b6 b5 b4 b3 b2 b1 b0 56 writing a nonzero value forces a calibration table 5-15. reset address b7 b6 b5 b4 b3 b2 b1 b0 57 writing a nonzero value forces a reset
22 at42qt1070 [datasheet] 9596c?at42?05/2013 6. specifications 6.1 absolute maximu m specifications 6.2 recommended op erating conditions 6.3 dc specifications vdd ?0.5 to +6 v max continuous pin current, any control or drive pin 10 ma short circuit duration to ground, any pin infinite short circuit duration to vdd, any pin infinite voltage forced onto any pin ?0.5 v to (vdd + 0.5) v caution: stresses beyond those listed under absolute maximu m specifications may cause permanent damage to the device. this is a stress rating only and functional op eration of the device at thes e or other conditions beyond those indicated in the operational sections of this spec ification is not implied. ex posure to absolute maximum specification conditions for extended periods may affect device reliability. operating temperature ?40 o c to +85 o c storage temperature ?55 o c to +125 o c vdd +1.8 v to 5.5 v supply ripple+noise 25 mv cx load capacitance per key 1 to 30 pf vdd = 3.3 v, cs = 10 nf, load = 5 pf, 32 ms default sleep, ta = recommended range, unless otherwise noted parameter description minimum typical maximum units notes vil low input logic level ? ? 0.2 vdd v vih high input logic level 0.7 vdd ? vdd + 0.5 v vol low output voltage ? ? 0.6 v voh high output voltage vdd ? 0.7v ? ? v iil input leakage current ? ? 1 a
23 at42qt1070 [datasheet] 9596c?at42?05/2013 6.4 power consumption measurements 6.5 timing specifications cx = 5 pf, rs = 4.7 k ? lp mode idd (a) at vdd = 5v 3.3 v 1.8 v 0 (8 ms) 1744 906 442 1 (16 ms) 1375 615 305 2 (24 ms) 1263 525 261 4 (32 ms) 1168 486 234 5 (40 ms) 1119 445 221 6 (48 ms) 1089 434 211 paramete r description minimum typica l maximum units notes t r response time di setting8ms ? lp mode + (di setting 8 ms) ms under host control f qt sample frequency 162 180 198 khz modulated spread-spectrum (chirp) t d power-up delay to operate/calibration time ? <230 ? ms can be longer if burst is very long. f i2c i 2 c clock rate ? ? 400 khz ? fm burst modulation, percentage 8 % ? reset pulse width 5 ? ? s ?
24 at42qt1070 [datasheet] 9596c?at42?05/2013 6.6 mechanical dimensions 6.7 at42qt1070-ssu ? 14-pin soic
25 at42qt1070 [datasheet] 9596c?at42?05/2013 6.8 at42qt1070-mmh ? 20-pin 3 3 mm vqfn
26 at42qt1070 [datasheet] 9596c?at42?05/2013 6.9 marking 6.9.1 at42qt1070-ssu ? 14-pin soic either part marking can be used. 1 pin 1 id 1070 1r5 date code description w=week code w week code number 1-52 where: a=1 b=2 .... z=26 then using the underscore a =27...z =52 date code abbreviated part number code revision 1.5, released 1 pin1id abbreviated part number code revision 1.5, released atmel qt1070 1r5 yyww yyww = date code, variable text
27 at42qt1070 [datasheet] 9596c?at42?05/2013 6.9.2 at42qt1070-mmh ? 20-pin 3 3 mm vqfn either part marking can be used. date code, released 42e 15 code revision 1.5, released shortened part number in hexadecimal 42e = 1070 pin 1 id date code description w=week code w week code number 1-52 where: a=1 b=2 .... z=26 then using the underscore a =27...z =52 date code, released 15 = code revision 1.5, released abbreviation of part number: (at42qt 1 0 70 -mmh) pin 1 id yzz = traceability code (variable text) y = the last digit of the year (for example 0 for year 2010, 1 for year 2011), zz is the trace code for each assembly lot. 170 15x yzz x = assembly location code (variable text)
28 at42qt1070 [datasheet] 9596c?at42?05/2013 6.10 part number 6.11 moisture sensitivity level (msl) part number description at42qt1070-ssu 14-pin soic rohs compliant ic at42qt1070-mmh 20-pin 3 x 3 mm vqfn rohs compliant ic msl rating peak body temperature specifications msl3 260 o c ipc/jedec j-std-020
29 at42qt1070 [datasheet] 9596c?at42?05/2013 appendix a. i 2 c operation the device communicates with the host over an i 2 c bus. the following sections give an overview of the bus; more detailed information is available from www.i2c-bus.org. devices are connected to the i 2 c bus as shown in figure a- 1 . both bus lines are connected to vdd via pull-up resistors. the bus drivers of all i 2 c devices must be open-drain type. this implements a wired and function that allows any and all devices to drive the bus, one at a time. a low level on the bus is generated when a device outputs a zero. figure a-1. i 2 c interface bus a.1 transferring data bits each data bit transferred on the bus is accompanied by a pulse on the clock line. the level of the data line must be stable when the clock line is high; the only exception to this rule is for generating start and stop conditions. figure a-2. data transfer device 1 device 2 device 3 device n r1 r2 vdd sda scl sda scl data stable data stable data change
30 at42qt1070 [datasheet] 9596c?at42?05/2013 a.2 start and stop conditions the host initiates and terminates a data transmission. the transmission is initiated when the host issues a start condition on the bus, and is terminated when the hos t issues a stop condition. between the start and stop conditions, the bus is considered busy. as shown in figure a-3 , start and stop conditions are signaled by changing the level of the sda line when the scl line is high. figure a-3. start and stop conditions a.3 address byte format all address bytes are 9 bits long, consisting of 7 address bits, one read/write control bit and an acknowledge bit. if the read/write bit is set, a read operation is performed, otherwise a write operation is performed. when the device recognizes that it is being addressed, it will acknowledge by pulling sda low in the ninth scl (ack) cycle. an address byte consisting of a slave address and a read or a write bit is called sla+r or sla+w, respectively. the most significant bit of the address byte is transmitted first. the address sent by the host must be consistent with that selected with the option jumpers. figure a-4. address byte format sda scl start stop addr msb addr lsb r/w ack sda scl start 12 789
31 at42qt1070 [datasheet] 9596c?at42?05/2013 a.4 data byte format all data bytes are 9 bits long, consisting of 8 data bits and an acknowledge bit. during a data transfer, the host generates the clock and the start and stop conditions, while the receiver is responsible for acknowledging the reception. an acknowledge (ack) is signaled by the receiver pulling the sda line low during the ninth scl cycle. if the receiver leaves the sda line high, a nack is signaled. figure a-5. data byte format a.5 combining address and data bytes into a transmission a transmission consists of a start condition, an sla+r/ w, one or more data bytes and a stop condition. the wired anding of the scl line is used to implement hands haking between the host and the device. the device extends the scl low period by pulling the scl line low whenever it needs extra time for processing between the data transmissions. note: each write or read cycle must end with a stop condition. the device may not respond correctly if a cycle is terminated by a new start condition. figure a-6 shows a typical data transmission. note that several data bytes can be transmitted between the sla+r/w and the stop. figure a-6. byte transmission data msb data lsb ack aggregate sda scl from master 12 789 sda from transmitter sda from receiver data byte stop or data byte next sla+r/w data msb data lsb ack 12 789 addr msb addr lsb r/w ack sda scl start 12 789 sla+rw data byte stop
32 at42qt1070 [datasheet] 9596c?at42?05/2013 associated documents ? qtan0062 ? qtouch and qmatrix sensitivity tuning for keys, slider and wheels ? touch sensors design guide revision history revision number history revision a ? october 2010 initial release of document for code revision 1.5 revision b ? november 2012 general updates revision c ? may 2013 applied new template
33 at42qt1070 [datasheet] 9596c?at42?05/2013 notes
atmel corporation 1600 technology drive san jose, ca 95110 usa tel: (+1) (408) 441-0311 fax: (+1) (408) 487-2600 www.atmel.com atmel asia limited unit 01-5 & 16, 19f bea tower, millennium city 5 418 kwun tong roa kwun tong, kowloon hong kong tel: (+852) 2245-6100 fax: (+852) 2722-1369 atmel mnchen gmbh business campus parkring 4 d-85748 garching bei mnchen germany tel: (+49) 89-31970-0 fax: (+49) 89-3194621 atmel japan g.k. 16f shin-osaki kangyo bldg 1-6-4 osaki, shinagawa-ku tokyo 141-0032 japan tel: (+81) (3) 6417-0300 fax: (+81) (3) 6417-0370 ? 2013 atmel corporation. all rights reserved. / rev.: 9596c?at42?05/2013 disclaimer: the information in this document is provided in conn ection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. exc ept as set forth in the atmel terms and conditions of sales locat ed on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, bu t not limited to, the implied warranty of merchantability, fitness for a particular purp ose, or non-infringement. in no event shall atmel be liable f or any direct, indirect, consequential, punitive, special or incide ntal damages (including, without limitation, damages for loss and profits, business i nterruption, or loss of information) arising out of the us e or inability to use this document, even if at mel has been advised of the possibility of suc h damages. atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the ri ght to make changes to specifications and products descriptions at any time without notice. atmel does not make any commitment to upda te the information contained herein. unless specifically provide d otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel products are not intended, authorized, or warranted for use as components in applicatio ns intended to support or sustain life. atmel ? , atmel logo and combinations thereof, adjacent key suppression ? , aks ? , qtouch ? , and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be registered trademarks or trademarks of others.

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